A power metal-oxide-semiconductor field-effect transistor (MOSFET) and an insulated gate bipolar transistor (IGBT) are widely used as a power control transistor. A protection circuit, including clamp diodes or zener diodes, is often used for a gate of such transistor, to improve resistance to a surge voltage caused by electrostatic discharge or an externally-connected inductor, for example. Patent Literatures (PTLs) 1 and 2 disclose a semiconductor device including such protection circuit.
The semiconductor device disclosed in PTL 1 includes a semiconductor element serving as an active element, first and second main terminals connected to the semiconductor element and a power supply, a control terminal controlling a current flowing between the first and second main terminals, voltage-dividing elements arranged between the first main terminal and the control terminal and dividing a voltage therebetween, and a voltage detection terminal outputting a voltage divided by the voltage-dividing elements. More specifically, the semiconductor device includes clamp diodes corresponding to zener diodes between a collector and a gate of the IGBT, and a dedicated area is arranged for these clamp diodes.
The semiconductor device disclosed in PTL 2 includes at least an area of one conductivity type formed approximately in the center of polysilicon having one plane. In addition, the semiconductor device includes at least a plurality of areas of the other conductivity type and a plurality of areas of one conductivity type alternately arranged to surround the area of one conductivity type. In this semiconductor device, the area of one conductivity type formed approximately in the center is connected to a source or a drain of a transistor, and the outermost area of one conductivity type or the other conductivity type is connected to the drain or the source of the transistor. In addition, an area of one conductivity type or the other conductivity type arranged between the area formed approximately in the center and the outermost area is connected to the gate of the transistor.
More specifically, as illustrated in FIG. 19, gate-drain clamp diodes 109 are collectively arranged inside gate-source zener diodes 110. Hereinafter, only a main portion relating to arrangement of this protection circuit will be described. A source wiring 112 is connected to an N+ type layer located at one end of the gate-source zener diodes 110 via an opening 121. A gate wiring 111 is connected to an N+ type layer located at the other end of the gate-source zener diodes 110 and at one end of the clamp diodes 109 via an opening 114. A drain wiring 117 is connected to an N+ type layer (a rectangular N+ type layer at the center) located at another end of the clamp diodes 109 via an opening 118. The source wiring 112, the gate wiring 111, and the drain wiring 117 are formed as aluminum wirings in the same layer. For connection to the clamp diodes 109, the drain electrode aluminum (drain wiring 117) is extended from an outer periphery of the chip to a center portion of the clamp diodes 109. In addition, the drain electrode aluminum (drain wiring 117) is arranged in a horizontal U shape. A bonding pad 113 for the gate wiring is arranged in a center portion surrounded by the horizontal U-shaped drain wiring 117.
In this semiconductor device, a plurality of areas of one conductivity type and a plurality of areas of the other conductivity type are alternately arranged to surround an area of one conductivity type located approximately in the center of polysilicon. In this way, diodes having a long junction length can be obtained without excessively increasing the chip dimension. In addition, by connecting the areas located approximately in the center of polysilicon and the outermost area of polysilicon to the source and the drain of the transistor and by connecting an area arranged between these areas to the gate of the transistor, a diode can be arranged between the gate and the source and between the gate and the drain of the transistor, without excessively increasing the chip dimension.
[PTL 1]
Japanese Patent Kokai Publication No. JP2001-244463A
[PTL 2]
Japanese Patent Kokai Publication No. JP 08-172190A